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78M6631 3 - phase power - measurement ic data sheet ds_66 31_056 rev 1 1 description the teridian ? 78M6631 is a highly integrated 3 - phase power measurement and monitoring system -on- chip (so c ) , with a 10 mhz 8051- compatible mpu core and single converter technology ? containing a 22- bit delta - sigma converter and 32- bit compute engine (ce) . the 78M6631 has been designed specifically for a wide variety of applicatio ns requiring 3 - phase power and quality measurements. it support s both delta and wye configurations. at the measurement interface, the device provides s ix analog inputs including three differential c urrent and three v oltage for interfacing to current and voltage sensors. the device provides better than 0.5% accuracy over a wide 2000:1 dynamic range. the integrated mpu core and 128 kb of f lash memory provide a flexible means of configuration, post - processing, data formatting, interfacing to host processor via a uart or spi interface, or using dio pins for led s or relay control . complete firmware is available from maxim and can be loaded int o the ic during manufacturing test. features ? < 0. 5 % watt accuracy over 2000:1 current range and over tem perature ? exceeds iec 62053 / ansi c12.20 standards ? voltage r eference < 40 ppm/c ? six a nalog i nputs s upporting 3- phase voltage and cu rrent measurement input s ? pin - or bi s electable delta or wye c onfiguration ? 22-b it d elta -s igma adc with in dependent 32 - bit compute en gine (ce) ? 8 -b it mpu (80515), one clock cy cle per i nstruction with 4 kb mpu xram ? 128 kb flash with s ecurity ? 32 khz time b ase with hardware watchdog timer ? uart , i 2 c, and h igh - speed slav e spi host interface options ? 17 general - purpose 5 v tol erant i/o pi ns ? packaged in a rohs - complian t (6/6) lead (pb)- fre e 56-p in t qfn ? applicati on firmware includes ( p er phas e) : o tr ue rms c u rrent and voltage cal culations o active, reactive, apparent, fundamental, and harmonic power calcul ations o fundamental and harmonic cur rent and voltage calcu lations o line f requency and power factor calc ulations o phase c ompensation ( 18 at 60 h z) o built -in calibration rou tines o programmable alarm thres holds o command lin e ( uart ) c ommunications o high -sp eed spi co mmunications teridian is a trademark and single converter technology is a registered trademark of maxim integrated products, inc. 19 - 6039; rev 1 ; 1 / 12 www.datasheet.co.kr datasheet pdf - http://www..net/
78M6631 data sheet ds_6631_056 2 rev 1 table of contents 1 hardware functional description ................................................................................................. 5 1.1 hardware overview ................................................................................................................. 5 1.2 device reset .......................................................................................................................... 7 1.3 power management ................................................................................................................ 7 1.3.1 voltage regulator ........................................................................................................ 7 1.3.2 power fault management ............................................................................................ 7 1.4 analog front - end (af e) .......................................................................................................... 8 1.4.1 analog current and voltage inputs .............................................................................. 8 1.5 digital computation engine (ce) ............................................................................................. 9 1.6 80515 mpu core .................................................................................................................. 10 1.6.1 sfrs ......................................................................................................................... 10 1.7 ram ..................................................................................................................................... 10 1.8 ioram .................................................................................................................................. 10 1.9 flash ..................................................................................................................................... 10 1.9.1 program security ....................................................................................................... 10 1.10 osc illator ............................................................................................................................... 11 1.11 pll and internal clock generation ........................................................................................ 11 1.12 real - time clock (rtc) ......................................................................................................... 11 1.13 hardware watchdog timer .................................................................................................... 11 1.14 temperature sensor ............................................................................................................. 12 1.15 general purpose digital i/o ................................................................................................... 12 1.16 d/ y selection pin .................................................................................................................. 12 1.17 eeprom interface ................................................................................................................ 12 1.18 spi slave port ...................................................................................................................... 12 1.19 test port ............................................................................................................................... 13 1.20 uart .................................................................................................................................... 13 1.21 in circuit emulator (ice) port ................................................................................................ 14 2 electrical specifications .............................................................................................................. 15 2.1 absolute maximum ratings ................................................................................................... 15 2.2 recommended external components ................................................................................... 16 2.3 recommended operating conditions .................................................................................... 16 2.4 performance specifications ................................................................................................... 17 2.4.1 input logic levels ..................................................................................................... 17 2.4.2 output logic levels ................................................................................................... 17 2.4.3 power - fault com parator ........................................................................................... 17 2.4.4 power supply monitor ............................................................................................... 18 2.4.5 supply current .......................................................................................................... 18 2.4.6 crystal oscillator ....................................................................................................... 18 2.4.7 temperature sensor .................................................................................................. 19 2.4.8 vref ........................................................................................................................ 19 2.4.9 adc converter, v3p3a referenced .......................................................................... 20 2.5 timing specifications ............................................................................................................ 21 2.5.1 flash memory ........................................................................................................... 21 2.5.2 eeprom interface .................................................................................................... 21 2.5.3 reset ...................................................................................................................... 21 2.5.4 spi slave port ........................................................................................................... 22 3 packaging .................................................................................................................................... 23 3.1 56- pin qfn package ............................................................................................................ 23 3.2 pinout ................................................................................................................................... 23 3.2.1 56- pin qfn package outline ..................................................................................... 24 3.2.2 recommended pcb land pattern for the qfn - 56 package ...................................... 25 4 pi n descriptions .......................................................................................................................... 26 www.datasheet.co.kr datasheet pdf - http://www..net/
ds_6631_056 78M6631 data sheet rev 1 3 4.1 power and ground pins ........................................................................................................ 26 4.2 analog pins ........................................................................................................................... 26 4.3 digital pins ............................................................................................................................ 27 5 i/o equivalent circuits ................................................................................................................. 28 6 ordering information ................................................................................................................... 29 7 contact information ..................................................................................................................... 29 revision history .................................................................................................................................. 30 www.datasheet.co.kr datasheet pdf - http://www..net/
78M6631 data sheet ds_6631_056 4 rev 1 figures figure 1: 78M6631 ic functional block diagram ..................................................................................... 6 figure 2: afe block diagram ................................................................................................................... 8 figure 3: functions defined by v1 ......................................................................................................... 11 figure 4: spi slave port: typical read and write operations ................................................................ 13 figure 5: spi slave port timing ............................................................................................................. 22 figure 6: pinout for qfn - 56 package .................................................................................................... 23 fig ure 7: pcb land pattern for qfn - 56 package .................................................................................. 25 figure 8: i/o equivalent circuits ............................................................................................................. 28 tables table 1: spi command description ....................................................................................................... 13 table 2: absolute maximum ratings ...................................................................................................... 15 table 3: recommended external components ...................................................................................... 16 table 4: recommended operating conditions ....................................................................................... 16 table 5: input logic levels .................................................................................................................... 17 table 6: output logic levels ................................................................................................................. 17 table 7: power - fault comparator performance specifications ............................................................... 17 table 8: power supply monitor performance specifications ( bme = 1) .................................................... 18 table 9: supply cu rrent performance specifications .............................................................................. 18 table 10: crystal oscillator performance specifications ......................................................................... 18 table 11: temperature sensor perf ormance specifications ................................................................... 19 table 12: vref performance specifications .......................................................................................... 19 table 13: adc converter performance specifications ........................................................................... 20 table 14: flash memory timing specifications ...................................................................................... 21 table 15: eeprom interface timing ..................................................................................................... 21 table 16: reset timing ....................................................................................................................... 21 table 17: spi slave port timing ............................................................................................................ 22 table 19: power and ground pins ......................................................................................................... 26 table 20: analog pins ............................................................................................................................ 26 table 21: digital pins ............................................................................................................................. 27 table 22: o rdering information .............................................................................................................. 29 www.datasheet.co.kr datasheet pdf - http://www..net/
ds_6631_056 78M6631 data sheet rev 1 5 1 hardware functional description 1.1 hardware overview the teridian 78M6631 single - chip power measurement and monitoring device integrate s all the primary ac measurement and control blocks required to i mplement the 3 - phase power measurement and monitoring system. the 78M6631 includes: ? six input a nalog front -end (afe) (3 differential current / 3 voltage) ? i ndependent digital computation engine (ce) ? 8051- compatible microprocessor (mpu) which exe cutes one inst ruction per clock cycle (80515) ? p recision voltage reference ? t emperature sensor ? ram and f lash memory ? a variety of i/o pi ns ? communication interfaces: uart, spi , and i 2 c (master) various current sensor technologies are supported inclu ding curr ent transformers (ct) , res istive shunts , and rogowski coil s . t he 32- bit compute engine (ce) of the 78M6631 sequentially process the samples from the analog inputs on pins ia, ib, ic, va, vb , and vc and performs cal culations to measure active power (watts) , reactive power (vars ) , apparent power (vas), power factor, fundamental power, and harmonic power for three independent phases. rms, fundamental, and harmonic currents and voltages are also computed for each phase. totals are available for most results. figure 1 provides a block diagram of the 78M6631 ic . a detailed description of the various functional blocks follows . refer to the applicable firmware description document for additional supported f unctionality. www.datasheet.co.kr datasheet pdf - http://www..net/
78M6631 data sheet ds_6631_056 6 rev 1 ? adc converter vref muxp xin xout vref reset v 1 uart tx rx digital i / o power fault gndd v 3 p 3 a v 3 p 3 d volt reg 2.5v to logic tmuxout faultz gnda vbias temp osc ( 32 . 768 khz ) mck pll vref cktest test mode e _ rxtx rtc vbias ice _ e test mux v 3 p 3 d ce _ prog ck _ ce ck _ mpu 80 mhz vadc ce multi - purpose io rtm rpulse wpulse dio _ 4 ... to tmux spi slave eeprom i / f flash 128 kb xram 4 kb ce _ data pcsz pclk psdi psdo sdata sdck sfr 80515 mpu emulator e _ tclk e _ rstz e _ rxtx e _ tclk e _ rst r p u l s e w p u l s e xram bus 8 16 32 cktest ice _ e cktesti pclk psdo pcsz psdi fir vb vc va xpulse ypulse x p u l s e y p u l s e ibn icp icn ibp iap ian dio3 dio4/sdck dio5/sdata dio6 dio8 dio9 d/y dio11 dio17 dio24 dio25 dio45 dio47 v3p3 sys vbat dio51 dio53 dio30 dio55 dio29 figure 1 : 78M6631 ic functional block diagram www.datasheet.co.kr datasheet pdf - http://www..net/
ds_6631_056 78M6631 data sheet rev 1 7 1.2 device reset when the reset pin is pulled high, all digital activity stops. only t he oscillator and rtc module continue to run. addition ally, all io ram bits are set to their default states. as long as v1 ( the input v oltage at the power fault block) is greater than vbias, the internal 2.5 v regulator continue s to provide power to the digital section. once initiated, the reset mode persist s until the reset timer times out. this occur s in 4 096 cycles of the crystal clock after reset goes low, at which time the mpu begin s executing it s pre boot and boot sequences from address 0x00 00. 1.3 power management 1.3.1 voltage regulator the 78M6631 provides an on - chip voltage regulator to create a 2.5 v supply for the digital logic. this regulator can be run off of the v3p3sys or vbat inputs depending upon power availability. 1.3.2 power fault management the 78M6631 provides for both hardwar e and software controlled power fault management. the v1 pin is connected to a comparator to monitor system power fault conditions. when the input to the comparator falls (v1 < vbias) the device can enter a brownout mode , if supported in firmware and the re is sufficient voltage on vbat , that reduces the mpu rate to 32 khz and disables all the measurement front - end circuits. if the overhead on vbat is insufficient to maintain a brownout mode , then the device can also attempt to enter a sleep mode where only rtc functions are active. if there is not sufficient voltage on vbat (or it is not supported) , then the part enter s reset mode when the comparator fails . www.datasheet.co.kr datasheet pdf - http://www..net/
78M6631 data sheet ds_6631_056 8 rev 1 1.4 analog front - end (afe) the afe functions as a data acquisition sys tem, controlled by t he mpu. the main blocks in the afe consist of an input multiplexer, a delta - sigma a/d converter, a fir decimation filter and a voltage reference. the metrology input signals (i ap, ian, ibp, ibn, icp, icn , va, vb, vc, and temp ) are multiplexed before be ing s ampled by the adc. the adc output is decimated by the fir filter and the resul ts are stored in ram where they can be accessed by the ce and the mpu. the functionality of the afe is established for various system requirements with different ce co de. afe programmability includes, but is not limited to : ? input m ultiplexer settings ? voltage supply and t emperature monitor inputs ? adc sampling rate ? fir length/resolution va vb mux vref 4.9152 mhz vbias cross ck32 vref mux ctrl vc mux v3p3a fir vbias ? adc converter + - vref temp v3p3d fir_done fir_start ibp ibn icp icn iap ian - + - + - + figure 2 : afe block diagram 1.4.1 analog current and voltage inputs with all ce code implementations for the 78M6631, p ins i ap , ian, ibp, ibn, icp, icn, va, vb, and vc are analog inputs to the afe for measuring current and voltage. various current sensor technologies can be supported i ncludin g current transformers, resist ive shunts , and rogowski coils . www.datasheet.co.kr datasheet pdf - http://www..net/
ds_6631_056 78M6631 data sheet rev 1 9 1.5 digital computation engine (ce) the ce, a dedicated 32 - bit digital signal processor, performs the back -end computations . ce calculations include: ? gain and o ffset compensation ? d elay compensation on all channels ? 90 phase shift for var calculations ? frequency measurement ? accumulatio n for voltage and current rms and power computation ? active, reactive, apparent, fundamental, and har monic power calculation ? fundamental and h armonic cur rent and voltage calculations ? monitoring of the input signal frequency (for frequency and phase information) ? monitoring of the input signal amplitude (for sag detection) ? temperature acquisition due to the custom nature and complexity of the ce, the c e code is part of the installed firmware and is not modified by the user. c ontact maxim support for more information regarding ce code . www.datasheet.co.kr datasheet pdf - http://www..net/
78M6631 data sheet ds_6631_056 10 rev 1 1.6 80515 mpu core the 78M6631 inc ludes an 80515 mpu (8 - bit, 8051- compatible) that processes most instructions in one clock cycle. the 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. normally , a machine cycle is aligned with a memory fetch, therefore, most of the 1 - byte instructions are performed in a single machine cycle (mpu clock cycle) . this leads to an 8x average p erformance improve ment (in terms of mips) over the intel 8051 device running at the same clock frequency . 1.6.1 sfr s several custom special function registers (sfr) are implemented in the 78m66 31 s 80515 mpu. refer to the 78m66 31 programmers reference manual for more information regarding the mapping of functionality to specific sfr and ioram addresses. 1.7 ram the ce and mpu share a single , general purpose 4kb ram (also referred to as xram) for data . the xram is natively accessible as 32 - bit words from the ce and on 8- bit boundaries from the cpu. the xram is accessed by the cpu through addresses 0x0000 to 0x0fff. 1.8 io ram the mpu accesses most of its external input and output f unctionality as well as programmable functionality through memory mapped io (ioram). the ioram is accessed by the cpu as data addresses 0x2000 to 0x20ff. 1.9 f lash the 78M6631 includes 128 kb of on - chip f lash memory. for read/write access from the cpu, t he flash is broken into four 32 kb banks that are managed by sfr settings. for erasing of the f lash memo ry from the cpu , the flash is segmented into individual 1024- byte pages and also controlled by sfr settings. 1.9.1 program security the 78M6631 has functio nality to guarantee the security of the users mpu and ce program code. when enabled, the security feature limits the ice to global f lash erase operations only. all other ice operations are blocked. security is enabled by mpu code that is executed in a pre - boot interval before the primary boot sequence begins. once security is enabled, the only way to disable it is to perform a global erase of the f lash , followed by a chip reset. www.datasheet.co.kr datasheet pdf - http://www..net/
ds_6631_056 78M6631 data sheet rev 1 11 v3p3 v3p3 - 400mv v3p3 - 10mv vbias 0v battery modes normal operation, wdt enabled wdt dis- abled v1 1.10 oscillator the 78M6631 oscillator drives a standard 32.768 khz quart z crystal . these crystals are accurate and do not require a high - current oscillator circuit . the 78M6631 oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capabilit y. the oscillator is powered directly and only from v3p3d , which therefore must be connected to a dc voltage source not to exceed 4 v . since the oscillator is self - biasing, an external resistor must not be connected across the crystal. 1.11 pll and inte rnal clock generation timing for the device is derived from the 32.768 khz crystal oscillator output. the pll and on - chip timing functions provide several clocks which include: ? the mpu clock (ckmpu) ? the emulator clock (2 x ckmpu) ? the clock for the ce (c kce) ? the delta - sigma adc and fir clock(ckadc, ckfir) these internal clocks can be adjusted for various programmable rates which affect device functionality. refer to the 78m66 31 programmers reference manual for more information regarding the progra mmability of the 78M6631 pll and internal clock generation modules. 1.12 real - time clock (rtc) the rtc circuit is driven directly by the crystal oscillator. the rtc consists of a counter chain and output registers. the counter chain consists of registers f or seconds, minutes, hours, day of week, day of month, month, and year (including leap years ). refer to the 78M6631 programmers reference manual for more information regarding the use of the 78M6631 rtc. 1.13 hardware watchdog timer in addition to the basic watchdog timer included in the 80515 mpu, an independent, robust, fixed - duration, watchdog timer (wdt) is included in the device. it uses the crystal oscillator as its time base and must be refreshed by the mpu firmware at least every 1.5 seconds. when not refreshed on time the wdt overflows, and the part is reset as if the reset pin were pulled high, except that the io ram bits are maintained. 4096 oscillator cycles (or 125 ms) after the wdt overflow, the mpu is launched from progr am address 0x0000. asserting ice_e deactivate s the wdt. the wdt can also be disabled by connecting the v1 pin to v3p3 d . t his also deactivates v1 power fault detection. since there is no method in firmware to disable the crystal oscilla tor or the wdt, it is guaranteed that whatever state the part might find itself in, upon watchdog overflow, the part is reset to a known state. figure 3 : functions defined by v1 www.datasheet.co.kr datasheet pdf - http://www..net/
78M6631 data sheet ds_6631_056 12 rev 1 1.14 temperature sensor the device includes an on- chip temperature sensor for determining the temperature of the bandgap re ference. the primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system . 1.15 general - purpose digital i/o the 78M6631 in cludes 17 general - purpose digital i/o pins . a s inputs, these pins are 5v compatible (no current - limiting resistors are needed). on reset or power - up, all dio pins are inputs . their input/output direction s are subsequently set by t he mpu. the d igital i/o pins can be categorized as follows: ? dio3 (1 pin) dio pin ? dio4, dio5 ( 2 pins ) dio/ eeprom ? dio6 (1 pin) dio pin ( m ultifunction) ? dio8, dio9, dio11 (3 pins) dio pins ? dio17 ( 1 pin) dio pin ? dio2 4, dio2 5 ( 2 pins) dio pins ? dio29, d io30 ( 2 pins) dio pins ? dio45, dio47 ( 2 pins ) dio pins ? dio51 ( 1 pin) dio pin ? dio53, dio55 ( 2 pins ) dio pins 1.16 d/ y selection pin the d / y pin selects either the delta or the wye configuration. at power - on, the delta/wye selection register assume s the s tate of the d/ y pin. the register value can be modified by the software overriding the state of the d/ y pin. 1.17 eeprom interface the 78M6631 provide s hardware support for a n optional 2 - pin or a 3 - wire ( microwire ? ) eepr om interfa ce. 2 - pin eeprom interface the dedicated 2 - pin serial interface communicates with external eeprom devices . the interface is multiplexed onto the dio4 (s d ck) and dio5 (sda ta ) pins . 3 - wire ( microwire ) e eprom interface a 500 khz three - wire interface, using sdata, s d ck and a dio pin for cs , is also available . 1.18 spi slave port the slave spi port communicates directly with the mpu data bus and is able to directly read and write x ram and io ram locations . it is also able to send commands to the mpu . the interface to the slave port consists of the pcsz, pclk, psdi , and psdo pins . a typical spi transaction is as follows . while pcsz is high, the port is held in an initialized/reset state . during this state, psdo is held in h i gh- z state and all transitions on pclk and psdi are ignored. when pcsz falls, the port begin s the transaction on the first rising edge of pclk . a transaction consists of an 8 - bit command, a 16- bit address , and then one o r more bytes of data . the transaction ends when pcsz is raised . some transactions can consist of a command only . the last spi command and a ddress (if part of the command) are available in the ioram. the spi port supports data transfers at up to 1 mb p s . the spi commands are described in table 1 and figure 4 illustrate s the spi interface read and write timing. microwire is a trademark of national semiconductor. www.datasheet.co.kr datasheet pdf - http://www..net/
ds_6631_056 78M6631 data sheet rev 1 13 table 1 : spi command description command description 11xx xxxx addr d0 ... d n output data on psdo is read from ram starting with byte at addr. addr auto increment s until pcsz is raised. mpu spi interrupt is generated . 1100 0000 addr d0 ... d n output data on psdo is read from ram starting with byte at addr. addr auto increment s until pcsz is raised. no mpu spi interrupt is generated . 1 0 xx xxxx addr d0 ... d n input data on psdi is written to ram starting with byte at addr. addr auto increment s until pcsz is raised. mpu spi interrupt is generated . 1 0 00 0000 addr d0 ... d n input data on psdi is written to ram starting with byte at addr. addr auto increment s until pcsz is raised. no mpu spi interrupt is generated . cmd addr d0 ... d n cmd and addr are available to the cpu in ioram . d0 dn are ignored. mpu spi inte rrupt is generated . a15 a14 a1 a0 c0 0 31 x d7 d6 d1 d0 d7 d6 d1 d0 c5 c6 c7 x pcsz psck psdi psdo 8 bit cmd 16 bit address data[addr] data[addr+1] 7 8 23 24 32 39 extended read . . . serial read a15 a14 a1 a0 c0 0 31 c5 c6 c7 x pcsz psck psdi psdo 8 bit cmd 16 bit address data[addr] data[addr+1] 7 8 23 24 32 39 extended write . . . serial write d7 d6 d1 d0 d7 d6 d1 d0 x hi z hi z (from host) (from 6531) (from host) (from 6531) figure 4 : spi slave port : typical r ead and w rite o perations since the addresses are in 16 - bit format, any type of xram da ta can be accessed: ce, mpu , or ioram but not sfrs or th e 80515- internal register bank . 1.19 test port one out of 16 digital or eight analog signals can be selected to be output on the tmuxout pin. refer to the 78m66 31 programmers reference manual for more information regarding the use of tmuxout. 1.20 uart the 78M6631 includes one uart (uart0) that can be programmed to communicate with a variety of external device s. the uart is a dedicated 2 - wire serial interfaces (no hardware flow control/handshaking), which can communicate at rates up to 38,400 b p s. a ll uart transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and xon/xoff options for variable communication baud rates from 300 to 38,400 bps. refer to the 78m66 31 programmers reference manual for more information regarding the use of the uart resources. www.datasheet.co.kr datasheet pdf - http://www..net/
78M6631 data sheet ds_6631_056 14 rev 1 1.21 in - circuit emulator (ice) port the 78m66 31 implements an in - circuit emulator (ice) port for debug and programming of the device. to enable the use of the port the ice_e pin must be pulled high. in this mode the e_ rst, e_tclk , and e_rxtx pins are enabled . c ontact maxim support for more information regarding the use of the ice interface for device programming and debug. www.datasheet.co.kr datasheet pdf - http://www..net/
ds_6631_056 78M6631 data sheet rev 1 15 2 e lectrical s pecifications 2.1 a bsolute m aximum r atings table 2 shows the absolute maximum ranges for the device. stresses beyond absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation at these or any other condition s beyond those indicated under recommended operatin g conditions ( section 2 .3 ) is not implied. exposure to absolute - maximum - rated conditions for extended periods may affect device reliability. all voltages are with respect to gnda. table 2 : absolute maximum ratings voltage and current supplies and ground pins v3p3d , v3p3a - 0.5 v to 4. 0 v gndd - 0.5 v to +0.5 v analog output pins vref -10 ma to +10 ma, - 0.5 v to ( v3p3a + 0.5 v) analog input pins iap, ian, ibp, ibn, icp, icn, va, vb, vc -10 m a to +10 ma - 0.5 v to ( v3p3a + 0.5 v ) xin, xout -10 ma to +10 ma - 0.5 v to 3.0 v all other pins configured as digital inputs -10 ma to +10 ma, - 0.5 to + 6 v configured as digital outputs -15 ma to +15 ma, - 0.5 v to ( v3p3d + 0.5 v) all other pins - 0.5 v to ( v3p3d + 0.5 v) temperature and esd stress operating junction temperature ( p eak , 100 ms) + 140c operating junction temperature ( c ontinuous ) + 125c storage temperature - 45c to +165c lead temperature ( s oldering , 10 s ) + 250c soldering tempe rature ( r eflow) +260 c esd st ress on all pin s 4 kv www.datasheet.co.kr datasheet pdf - http://www..net/
78M6631 data sheet ds_6631_056 16 rev 1 2.2 recommended external components table 3 : recommended external components name from to function value unit c1 v3p3a agnd bypass capacitor for 3.3 v supply 0.1 20% f c 3 v3p 3 d dgnd bypass capacitor for v3p3 d 1.0 30% f xtal xin xout 32.768 khz crystal , electrically similar to ecs .327 - 12.5- 17x or vishay xt26t, load capacitance 12.5 pf 32.768 khz cxs xin agnd load capac itor for crystal (depends on crystal specs and board parasitics) 33 10% pf cxl xout agnd load capacitor for crystal (depends on crystal specs and board parasitics) 15 10% pf notes: 1. agnd and dgnd should be connected together. 2. v3p3ds and v3p3a should be connected together. 2.3 r ecommended operating c onditions table 4 : recommended operating conditions p arameter condition min typ max unit v3p3 d , v3p3a : 3.3 v supply voltage ( v3p3a and v3p3d must be at the same voltage ) normal o per ation 3.0 3.3 3.6 v operating temperature range -40 +85 o c www.datasheet.co.kr datasheet pdf - http://www..net/
ds_6631_056 78M6631 data sheet rev 1 17 2.4 p erformance s pecifications 2.4.1 input logic levels table 5 : input logic levels p arameter c ondition m in t yp m ax u nit digital high - level input voltage 1 , v ih 2 v dig ital low - level input voltage 1 , v il 0.8 v input pull up current, i il e_rxtx, e_rst, cktest other digital inputs vin = 0 v, ice_e = 1 10 10 -1 0 100 100 + 1 a a a in put pull down current, i ih ice_e reset other digital inputs vin = v3p3d 10 10 -1 0 100 100 + 1 a a a 1 to reduce power consumption , digital inputs should be below 0.3 v or above 2.5 v to minimize supply current. 2.4.2 o utput logic levels table 6 : output logic levels p arameter c ondition m in t yp m ax u nit digital high - level output voltage v oh i load = 1 ma v3p3d - 0.4 v i load = 15 ma v3p3d - 0 .6 v digital low - level output voltage v ol i load = 1 ma 0 0.4 v i load = 15 ma 0.8 v 2.4.3 power - fault c omparator table 7 : power - fault comparator performance specifications p arameter c ondition min t yp max u nit offset voltage : v1 - vbias -20 +15 mv hysteresis current: v1 v in = vbias C 100 mv 0.8 1.2 a response time : v1 + 100 mv overdrive voltage at v1 rising voltage at v1 falling 10 8 37 100 100 s s wdt disable threshold: v1 - v3p3a -400 -10 mv www.datasheet.co.kr datasheet pdf - http://www..net/
78M6631 data sheet ds_6631_056 18 rev 1 2.4.4 power supply monitor table 8 : power supply monitor performance specifications ( bme = 1 ) p arameter c ondition m in typ max unit load resistor C 27 45 63 k lsb value [ m40mhz , m26mhz ] = [00], [10], or [11] fir_len =0 (l=138) fir_len =1 (l=288) (-10%) - 48.7 - 5.35 (+10%) p v p v [ m40mhz , m26mhz ] = [01] fir_len =0 (l=186) fir_len =1 (l=384) (-10%) - 19.8 - 2.26 (+10%) p v p v offset error - 200 0 +100 mv 2.4.5 s upply c urrent table 9 : supply current performance specifications p arameter c ondition m in t yp max unit v3p3 d current (ce off) normal o peration, v3p3a = v3p3sys = 3.3 v ckmpu = 614 khz no flash memory write rtm_e =0, eck_dis =1, adc_e =1, ice_e =0 4.2 6.35 ma v3p3 d current (ce on) 8.4 9.6 ma v3p3a current 3. 3 3.8 ma v3p3 d current, write flash normal o peration as above, e xcept write f lash at maximum rate, ce_e = 0, adc_ e = 0 9.1 12 ma 2.4.6 c rystal o scillator table 10 : crystal oscillator performance specifications p arameter c ondition min t yp max unit maximum output power to crystal 4 crystal connec ted 1 p w xin to xout capacitance 1 3 pf capacitance to dgnd 1 xin xout rtca_adj = 0 5 5 pf pf www.datasheet.co.kr datasheet pdf - http://www..net/
ds_6631_056 78M6631 data sheet rev 1 19 2.4.7 temperature s ensor table 11 shows the performance for the temperature sensor . the lsb values do not include the 8 - bit left shift at ce input. table 11 : temperature sensor performance specifications p arameter c ondition m in t yp max unit nominal relationship: n(t) = s n * (t - t n ) + n n , t n = 2 2 oc nominal sensitivity (s n ) 3 n 3 l 00107 . 0 s ? ? ? ? ? ? ? ? = [ m26 mhz , m40mh ] = [00], [ 0 1], or [11] fir_len = 0 (l=138) fir_len =1 (l=288) -104 -947 lsb/oc [ m26 mhz , m40 mhz ] = [ 1 0] fir_len =0 (l=186) -255 nominal offset (n n ) 4 3 n 3 l 510 . 0 n ? ? ? ? ? ? ? = [ m26 mhz , m40mh ] = [00], [ 0 1], or [11] fir_len =0 (l=138) fir_len =1 (l=288) 49641 451200 lsb [ m26 mhz , m40 mhz ] = [ 1 0] fir_len =0 (l=186) 121500 temperature error 2 ? ? ? ? ? ? + ? ? = n n n t s n t n t err ) ) ( ( t n = 2 2 c , t = - 40oc to +85oc -10 1 + 10 1 oc 1 guarante ed by design ; not production tested. 2 n n is measured at t n during measurement calibration and is stored in mpu or ce for use in temperature calculations. 2.4.8 vref table 12 shows the performance specificat i ons for vref . unless otherwise specified, vref_dis = 0 . table 12 : vref performance specifications p arameter c ondition m in t yp max unit vref output voltage, vref(22 ) t a = + 22oc 1.193 1.195 1.197 v vref chop step 4 0 mv vref p ower supply sensitivity vref / v3p3a v3p3a = 3.0 to 3.6 v - 1.5 + 1.5 mv/v vref input impedance vref_dis = 1 , vref = 1.3 to 1.7 v 100 k? vref output impedance cal =1, i load = 10 a, - 10 a 2.5 k? vnom definitio n 2 2 ) 22 ( 1 ) 22 ( ) 22 ( ) ( 2 tc t tc t vref t vnom ? + ? + = v vnom temperature coefficients : tc1 tc2 3.18 (52.46- trimt ) - 0.44 4 v /oc v /c 2 vref(t) deviation from vnom(t) ) 40 , 22 max( 10 ) ( ) ( ) ( 6 ? ? t t vnom t vnom t vref -40 1 +40 1 ppm /oc vref aging 25 ppm / year 1 guaranteed by design ; not production tested. 2 this relationship describes the nominal behavior of vref at different temperatures. www.datasheet.co.kr datasheet pdf - http://www..net/
78M6631 data sheet ds_6631_056 20 rev 1 2.4.9 adc converter , v3p3a referenced table 13 shows the pe rformance specifications for the adc converter, v3p3a referenced. for this data, fir_len = 0, vref_dis = 0 and lsb values do not include the 9 - bit left shift at the ce input. table 13 : adc converter performance specifications par ameter c ondition min t yp max unit recommended input range ( v in - v3p3a ) -250 + 250 mv peak voltage to current crosstalk ) cos( * 10 6 vcrosstalk vin vin vcrosstalk ? v in = 200 mv peak, 65 hz, on va . vcrosstalk = largest measurement on ia or ib -10 1 + 10 1 v/v thd (first 10 harmonics) 1 : 250 mv -pk 20 mv -pk v in = 65 hz, 64 kpts fft, blackman - harris window ckce = 5 mhz -75 1 -90 1 db db input impedance v in = 65 hz 40 90 k? temperature coefficient of input impedance v in = 65 hz 1.7 ? /c lsb size 3 3 75 . 4 25 . 1 ? ? ? ? ? ? ? ? = l v v ref lsb l = fir length [ m40mhz , m26mhz ] = [00], [10], or [11] nv/ lsb [ m40mhz , m26mhz ] = [01] nv/ lsb digital full scale 3 3 ? ? ? ? ? ? l l = fir length [ m40mhz , m26mhz ] = [00], [10], or [11] lsb [ m40mhz , m26mhz ] = [01] lsb a dc gain error versus %power supply variation 3 . 3 / 3 3 100 / 357 10 6 a p v v nv nout in pk ? ? v in = 200 mv pk, 65 hz , v3p3a=3.0 v, 3.6 v 50 ppm/% input offset ( v in - v3p3a ) -10 + 10 mv 1 guaranteed by desig n ; not production tested. www.datasheet.co.kr datasheet pdf - http://www..net/
ds_6631_056 78M6631 data sheet rev 1 21 2.5 t iming s pecifications 2.5.1 flash memory table 14: flash memor y timing specifications p arameter c ondition m in t yp max unit flash write cycles - 40c to +85c 20,000 cycles flash data retention + 25c 100 years flash data retention + 85c 10 years flash byte write operations between page or mass erase operations 2 cycles write time per byte 42 s page erase (1024 bytes) 20 ms mass erase 200 ms 2.5.2 ee prom i nterface table 15 : eeprom interface timing p arameter c ondition m in t yp max unit write clock frequency (i 2 c) ckmpu = 4.9152 mhz , u sing interrupts 78 khz ckmpu = 4.9152 mhz, bit - banging dio4/5 150 khz write clock frequency (3 - wire) ckmpu = 4.9152 mhz 500 khz 2.5.3 reset table 16 : reset timing p arameter c ondition min t yp max unit reset pulse width 5 s reset pulse fall time 1 1 s 1 guaranteed by design ; not production tested. www.datasheet.co.kr datasheet pdf - http://www..net/
78M6631 data sheet ds_6631_056 22 rev 1 2.5.4 spi slave p ort table 17 : spi slave port timing p arameter c ondition m in t yp max unit t spicyc pclk cycle time 1 s t spilead enable lead time 15 ns t spilag enable lag time 0 ns t spiw pclk pulse width high 40 ns low 40 t spisck pcsz to first pclk fall ignore if pclk is low when pcsz falls 2 ns t spidis disable time 0 ns t spiev pclk to data out 15 ns t spisu data input setup time 10 ns t spih data input hold time 5 ns msb out lsb out msb in lsb in t spicyc t spilead t spilag t spisck t spih t spiw t spiev t spiw t spidis pcsz pclk psdi psdo figure 5 : spi slave port timing www.datasheet.co.kr datasheet pdf - http://www..net/
ds_6631_056 78M6631 data sheet rev 1 23 3 p ackag ing 3.1 56- pin qfn package 3.2 pinout 1 teridian 78 m 6631 2 3 4 5 6 7 8 9 10 11 12 13 14 1 5 1 6 31 32 2 6 2 7 2 8 29 30 1 8 1 9 2 0 2 1 2 2 2 4 2 5 35 36 37 38 39 40 41 42 4 3 4 4 4 5 4 6 4 7 4 8 5 2 5 3 5 4 5 5 5 6 e_rxtx gndd tmuxout dio17 tx pclk cktest psdo pcsz v3p3sys dio5/sdata dio4/sdck rx reset vbat e_rst x o u t gndd x i n v 1 v r e f v 3 p 3 a gnda 1 7 dio3 2 3 33 34 4 9 5 0 5 1 e_tclk gndd v 3 p 3 d dio47 n/c dio29 n/c n/c psdi dio30 dio45 gndd dio25 dio51 dio53 dio55 dio24 dio8 ice_e dio9 dio11 d/y ian iap ibp ibn icp icn va vb vc dio6 figure 6 : pinout for qfn - 56 package www.datasheet.co.kr datasheet pdf - http://www..net/
78M6631 data sheet ds_6631_056 24 rev 1 3.2.1 56- pin qfn package outline www.datasheet.co.kr datasheet pdf - http://www..net/
ds_6631_056 78M6631 data sheet rev 1 25 3.2.2 recommended pcb land pattern for the qfn - 56 package figure 7 : pcb land pattern for qfn -56 package www.datasheet.co.kr datasheet pdf - http://www..net/
78M6631 data sheet ds_6631_056 26 rev 1 4 pin d escriptions 4.1 power and ground pins table 18 : power and ground pins name type circuit description gnda p C analog ground: this pin should be connected directly to the grou nd plane. gndd p C digital ground: this pin should be connected directly to the ground plane. v3p3a p C analog power supply: a 3.3 v power supply should be connected to this pin, must be the same voltage as v3p3sys. v3p3d p C system 3.3 v supply. th is pin should be connected to a 3.3 v power supply. 4.2 analog pins table 19 : analog pins name type circuit description iap, ian, ibp, ibn, icp, icn i 6 line current sense inputs: these pins are voltage inputs to the internal a/d con verter . typically, they are connected to the outputs of current sensors . unused pins must be connected to v3p3a . va, vb , vc i 6 line voltage sense inputs: these pins are voltage inputs to the internal a/d converter . typically, they are connecte d to the outputs of resistor dividers . unused pins must be connected to v3p3a. v1 i 7 comparator input: this pin is a voltage input to the internal comparator . the voltage applied to the pin is compared to the internal bias voltage (1.6 v). if the input voltage is above vbias, the comparator output is high (1) . if the comparator output is low, a voltage fault occur s . a series 5 k ? resistor should be connected from v1 to the resistor divider. vref o 9 voltage reference for the a dc. normally disabled and left unconnected . if en abled, a 0.1 f capacitor to v3p3 a should be connected to this pin. xin xout i 8 crystal inputs: a 32 khz crystal should be connected across these pins . typically, a 33 pf ca pacitor is also co nnected from xin to gnda and a 15 pf capacitor is connected from xout to gnda . it is important to mi nimize the capacitance between these pins . refer to the crystal manufacturer data sheet for details. if an external clock is used, a 150 mv p - p clock signal should be applied to xin, and xout should be left unconnected. 1) pin types: p = power, o = output, i = input, i/o = input/output the circuit number denotes the equivalent circuit, as specified under section 5 i/o equivalent circuits . www.datasheet.co.kr datasheet pdf - http://www..net/
ds_6631_056 78M6631 data sheet rev 1 27 4.3 digital pins table 20 : digital pins name type circuit description dio3 i/o 3, 4 dedicated dio pin. di o4 ,dio5,dio6 dio 8, dio9, dio 1 1 dio1 7 dio 24, dio25 dio29, dio30 dio45 , dio47 di o 51, dio53 dio55 i/o 3, 4, 5 multi - use pins, dio. (dio4 = sck, dio5 = sda when configured as eeprom interface; if unused, these pins must be con figured as dios and set to out puts by the firmware . d/ y i C selects either the delta or the wye configuration. pclk psdo pcsz psdi i/o 3, 4, 5 spi port. e_rxtx i/o 1, 4, 5 p ort pins (when ice_e pulled high). e_rst i/o 1, 4, 5 e_tclk o 4, 5 ice_e i 2 ice enable. when zero, e _rst, e_tclk and e_rxtx seg32 f or production units, this pin should be pulled to gnd to disable the emulator port. cktest i/o 3, 4 test clock. tmuxout o 4 digital test multiplexer output . controlled by t mux[3:0]. reset i 2 chip reset: this input pin i s used to reset the chip into a known state. for normal operation, this pin is pulled low. to reset the chip, this pin should be pulled high. this pin has an internal 30 a ( typ ) current source pull down. no external reset circuitry is necessary. rx i 3 uart input. if this pin is unused , it must be terminated to v3p3d or gndd. tx o 4 uart output. gndd (pin 55) i 7 enables production test. this pin must be grounded in normal operation. pin types: p = power, o = output, i = input, i/o = input/output. the circuit number denotes the equivalent circuit, as specified in section 5 , i/o equivalent circuits . www.datasheet.co.kr datasheet pdf - http://www..net/
78M6631 data sheet ds_6631_056 28 rev 1 5 i/o equivalent circuits oscillator equivalent circuit type 8: oscillator i/o digital input equivalent circuit type 1: standard digital input or pin configured as dio input with internal pull-up gndd 110k v3p3d cmos input v3p3d digital input pin digital input type 2: pin configured as dio input with internal pull-down gndd 110k gndd cmos input v3p3d digital input pin digital input type 3: standard digital input or pin configured as dio input gndd cmos input v3p3d digital input pin cmos output gndd v3p3d gndd v3p3d digital output equivalent circuit type 4: standard digital output or pin configured as dio output digital output pin lcd output equivalent circuit type 5: lcd seg or pin configured as lcd seg lcd driver gndd lcd seg output pin to mux gnda v3p3a analog input equivalent circuit type 6 : adc input analog input pin comparator input equivalent circuit type 7: comparator input gnda v3p3a to comparator comparator input pin to oscillator gndd oscillator pin vref equivalent circuit type 9: vref from internal reference gnda v3p3a vref pin v2p5 equivalent circuit type 10: v2p5 from internal reference gndd v3p3d v2p5 pin vlcd equivalent circuit type 11: vlcd power gndd lcd drivers vlcd pin vbat equivalent circuit type 12: vbat power gndd power down circuits vbat pin v3p3d equivalent circuit type 13: v3p3d from v3p3sys v3p3d pin from vbat 10 40 figure 8 : i/o equivalent circuits www.datasheet.co.kr datasheet pdf - http://www..net/
ds_6631_056 78M6631 data sheet rev 1 29 6 ordering information table 21: ordering information part part description (package) flash size packaging order number package marking 78M6631 56-pin qfn, lead(pb)- free 128 kb bulk 78M6631-im/f 78M6631-im tape and reel 78M6631-imr/f 7 contact information for more information about maxim products or to chec k the availability of t he 78M6631, contact technical support at www.maxim-ic.com/support . www.datasheet.co.kr datasheet pdf - http://www..net/
ds_6631_056 78M6631 data sheet 30 rev 1 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no cir cuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 201 2 maxim integrated products maxim is a registered trademark of maxim integrated products. revision history revision number revision date description pages changed 0 9 /11 initial release ? 1 1/12 removed information about programmed devices from table 21. ordering information 29 www.datasheet.co.kr datasheet pdf - http://www..net/

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